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INTEGRATED CIRCUITS
SSTV16857 14-bit SSTL_2 registered driver with differential clock inputs
Product data Supersedes data of 2002 Jun 05 2002 Sep 27
Philips Semiconductors
Philips Semiconductors
Product data
14-bit SSTL_2 registered driver with differential clock inputs
SSTV16857
FEATURES
* Stub-series terminated logic for 2.5 V VDDQ (SSTL_2) * Optimized for DDR (Double Data Rate) SDRAM applications * Inputs compatible with JESD8-9 SSTL_2 specifications. * Flow-through architecture optimizes PCB layout * ESD classification testing is done to JEDEC Standard JESD22. * Latch-up testing is done to JEDEC Standard JESD78, which * Same form, fit, and function as SSTL16877 * Full DDR 200/266 solution @ 2.5 V when used with PCKV857 * See SSTV16856 for driver/buffer version with mode select. * Available in TSSOP-48, TVSOP-48 and 56 ball VFBGA packages
DESCRIPTION
The SSTV16857 is a 14-bit SSTL_2 registered driver with differential clock inputs, designed to operate between 2.3 V and 2.7 V. VDDQ must not exceed VCC. Inputs are SSTL_2 type with VREF normally at 0.5*VDDQ. The outputs support class I which can be used for standard stub-series applications or capacitive loads. Master reset (RESET) asynchronously resets all registers to zero. The SSTV16857 is intended to be incorporated into standard DIMM (Dual In-Line Memory Module) designs defined by JEDEC, such as DDR (Double Data Rate) SDRAM or SDRAM II Memory Modules. Different from traditional SDRAM, DDR SDRAM transfers data on both clock edges (rising and falling), thus doubling the peak bus bandwidth. A DDR DRAM rated at 133 MHz will have a burst rate of 266 MHz. The modules require between 23 and 27 registered control and address lines, so two 14-bit wide devices will be used on each module. The SSTV16857 is intended to be used for SSTL_2 input and output signals. The device data inputs consist of differential receivers. One differential input is tied to the input pin while the other is tied to a reference input pad, which is shared by all inputs. The clock input is fully differential to be compatible with DRAM devices that are installed on the DIMM. However, since the control inputs to the SDRAM change at only half the data rate, the device must only change state on the positive transition of the CLK signal. In order to be able to provide defined outputs from the device even before a stable clock has been supplied, the device must support an asynchronous input pin (reset), which when held to the LOW state will assume that all registers are reset to the LOW state and all outputs drive a LOW signal as well. exceeds 100 mA. Protection exceeds 2000 V to HBM per method A114.
PIN CONFIGURATION
Q1 Q2 GND VDDQ Q3 Q4 Q5 GND VDDQ 1 2 3 4 5 6 7 8 9 48 D1 47 D2 46 GND 45 VCC 44 D3 43 D4 42 D5 41 D6 40 D7 39 CLK- 38 CLK+ 37 VCC 36 GND 35 VREF 34 RESET 33 D8 32 D9 31 D10 30 D11 29 D12 28 VCC 27 GND 26 D13 25 D14
Q6 10 Q7 11 VDDQ 12 GND 13 Q8 14 Q9 15 VDDQ 16 GND 17 Q10 18 Q11 19 Q12 20 VDDQ 21 GND 22 Q13 23 Q14 24
SW00685
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25C; tr =tf v2.5 ns SYMBOL tPHL/tPLH CI PARAMETER Propagation delay; CLK to Qn Input capacitance CONDITIONS CL = 30 pF; VDDQ = 2.5 V VCC = 2.5 V TYPICAL 2.4 2.9 UNIT ns pF
ORDERING INFORMATION
PACKAGES 48-Pin Plastic TSSOP 48-Pin Plastic TSSOP (TVSOP) 56-Ball Plastic VFBGA TEMPERATURE RANGE 0 to +70 C 0 to +70 C 0 to +70 C ORDER CODE SSTV16857DGG SSTV16857DGV SSTV16857EV DWG NUMBER SOT362-1 SOT480-1 SOT702-1
2002 Sep 27
2
Philips Semiconductors
Product data
14-bit SSTL_2 registered driver with differential clock inputs
SSTV16857
PIN DESCRIPTION
PIN NUMBER 34 48, 47, 44, 43, 42, 41, 40, 33, 32, 31, 30, 29, 26, 25 1, 2, 5, 6, 7, 10, 11, 14, 15, 18, 19, 20, 23, 24 35 3, 8, 13, 17, 22, 27, 36, 46 28, 37, 45 4, 9, 12, 16, 21 38 39 SYMBOL RESET NAME AND FUNCTION LVCMOS asynchronous master reset (Active LOW) SSTL_2 data inputs
LOGIC DIAGRAM
RESET VREF D1
REGISTER
Q1
D2
D1 - D14
REGISTER
Q2
D3
REGISTER
Q3
Q1 - Q14 VREF GND VCC VDDQ CLK+ CLK-
SSTL_2 data outputs
D4 REGISTER Q4
SSTL_2 input reference level
D5
Ground (0 V) Positive supply voltage Output supply voltage
D7 D6
REGISTER
Q5
REGISTER
Q6
Differential clock inputs
D8
REGISTER
Q7
REGISTER
Q8
FUNCTION TABLE
INPUTS RESET L H H H CLK X L or H CLK X L or H D X H L X OUTPUT Q L H L Q0
D12 REGISTER D10 REGISTER Q10 D9 REGISTER Q9
D11
REGISTER
Q11
Q12
H = High voltage level L = High voltage level = High-to-Low transition = Low-to-High transition X = Don't care
D13
REGISTER
Q13
D14 CLK+ CLK-
REGISTER
Q14
SW00763
2002 Sep 27
3
Philips Semiconductors
Product data
14-bit SSTL_2 registered driver with differential clock inputs
SSTV16857
BALL CONFIGURATION
1 2 3 4 5 6
A
Q1
NC
NC
NC
NC
D1
B
GND
Q2
VCC
VCC
D2
GND
C
Q4
Q3
Q5
D5
D3
D4
D
VCC
GND
Q6
CLK-
D6
D7
E
VCC
Q7
CLK+
VCC
F
GND
Q8
VREF
GND
G
VCC
GND
Q9
RESET
D9
D8
H
Q11
Q12
Q10
D10
D12
D11
J
GND
Q13
VCC
VCC
D13
GND
K
Q14
NC
NC
NC
NC
D14
SW00952
ABSOLUTE MAXIMUM RATINGS1
SYMBOL VCC IIK VI IOK VOUT IO OUT PARAMETER DC supply voltage DC input diode current DC input voltage3 DC output diode current DC output voltage3 DC output current Continuous current4 VO = 0 to VDDQ VCC, VDDQ, or GND VO < 0 VI < 0 CONDITION LIMITS MIN -0.5 -- -0.5 -- -0.5 -- -- MAX +4.6 -50 VDDQ + 0.5 -50 VDDQ + 0.5 50 100 UNIT V mA V mA V mA
Tstg Storage temperature range2 -65 +150 C NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 4. The continuous current at VCC, VDDQ, or GND should not exceed 100 mA.
2002 Sep 27
4
Philips Semiconductors
Product data
14-bit SSTL_2 registered driver with differential clock inputs
SSTV16857
RECOMMENDED OPERATING CONDITIONS1
SYMBOL VCC VDDQ VREF VTT VI VIH VIL VIH VIL IOH IOL PARAMETER Supply voltage Output supply voltage Reference voltage (VREF = 0.5 x VDDQ) Termination voltage Input voltage AC HIGH-level input voltage AC LOW-level input voltage DC HIGH-level input voltage DC LOW-level input voltage HIGH-level output current LOW-level output current All inputs All inputs All inputs All inputs TEST CONDITIONS MIN 2.3 2.3 1.15 VREF - 40 mV 0 VREF + 350 mV -- VREF + 180 mV VSS - 0.5 V -- -- 0 TYP 2.5 2.5 1.25 VREF -- -- -- -- -- -- -- -- MAX 2.7 2.7 1.35 VREF + 40 mV VCC -- VREF - 350 mV VDDQ + 0.5 V VREF - 180 mV -20 20 70 UNIT V V V V V V V V V mA mA C
Tamb Operating free-air temperature range NOTE: 1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL VIK VOH VO OL VCMR VPP PARAMETER I/O supply voltage HIGH level output voltage TEST CONDITIONS VCC = 2.3 V; II = -18 mA VCC = 2.3 V to 2.7 V; IOH = -100 A VCC = 2 3 V; IOH = -16 mA 2.3 16 VCC = 2.3 V to 2.7 V; IOL = 100 A VCC = 2.3 V; IOL = 16 mA Common mode range for reliable performance Minimum peak-to-peak input to ensure logic state VCC = 2.7 V; VI = 1.7 V or 0.8 V VCC = 2.7 V; VI = 2.7 V or 0 V VCC = 2.7 V; VI = 1.7 V or 0.8 V VCC = 2.7 V; VI = 2.7 V or 0 V VCC = 2.7 V VCC = 2.7 V; VI = 1.7 V or 0.8 V VCC = 2.7 V; VI = 2.7 V or 0 V VREF = 1 15 V or 1 35 V 1.15 1.35 VREF = 1 15 V or 1 35 V 1.15 1.35 VREF = 1.15 V or 1.35 V RESET = GND RESET = VCC Temp = 0 to +70 C MIN -- VCC - 0.2 1.95 1 95 -- -- 0.97 360 -- -- -- -- -- -- -- TYP2 -- -- -- -- -- -- -- 0.01 0.01 0.05 0.05 0.05 0.5 10 MAX -1.2 -- -- 0.2 0.35 1.53 -- 5 5 5 5 5 10 25 V V mV A A A A mA V UNIT
LOW level output voltage CLK, CLK CLK, CLK Data inputs RESET inputs,
II
CLK, CLK CLK VREF
ICC
Quiescent supply current CLK and CLK in opposite state1
NOTES: 1. When CLK and CLK are HIGH, typical ICC = 25 mA. 2. All typical values are at VCC = 2.5 V and Tamb = 25 C (unless otherwise specified).
2002 Sep 27
5
Philips Semiconductors
Product data
14-bit SSTL_2 registered driver with differential clock inputs
SSTV16857
TIMING REQUIREMENTS
Over recommended operating conditions; Tamb = 0 to +70 C (unless otherwise noted) (see Figure 1) LIMITS SYMBOL PARAMETER TEST CONDITIONS VCC = 2.5 V 0.2 V MIN fclock tw tsu th Clock frequency Pulse duration, CLK, CLK HIGH or LOW Data before CLK, CLK Setup time Hold time RESET HIGH before CLK, CLK -- 1.0 0.2 0.8 0.75 MAX 200 -- -- -- -- ns ns MHz ns UNIT
SWITCHING CHARACTERISTICS
Over recommended operating conditions; Tamb = 0 to +70 C; VDDQ = 2.3 - 2.7 V and VDDQ does not exceed VCC. Class I, VREF = VTT = VDDQ x 0.5 and CL = 10 pF (unless otherwise noted) (see Figure 1) LIMITS SYMBOL FROM (INPUT) Maximum clock frequency CLK and CLK RESET
184/200-pin DDR SDRAM DIMM
TO (OUTPUT)
VCC = 2.5 V 0.2 V MIN MAX -- 2.8 4.0 200
UNIT
fmax tPLH/tPHL tPHL
MHz ns ns
Q Q
1.0 2.0
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
FRONT SIDE SSTV16857 SSTV16857 PCKV857
The PLL clock distribution device and SSTV registered drivers reduce signal loads on the memory controller and prevent timing delays and waveform distortions that would cause unreliable operation
SDRAM
SW00686
2002 Sep 27
6
Philips Semiconductors
Product data
14-bit SSTL_2 registered driver with differential clock inputs
SSTV16857
PARAMETER MEASUREMENT INFORMATION AC WAVEFORMS
VIH CLK VREF VREF INPUT VIL tPLH tPHL VOH OUTPUT VREF VREF VOL VREF VREF VIL tW VIH
SW00339
Waveform 3. Pulse duration
SW00836
Waveform 1. Propagation delay times
VIH TIMING INPUT VIH RESET VREF VIL tPHL VOH OUTPUT VREF VOL DATA INPUT VREF VREF VIL tsu th VIH VREF VIL
SW00837 SW00340
Waveform 2. Propagation delay RESET to output. Waveform 4. Setup and hold times
TEST CIRCUIT
VTT 50 TEST POINT CL = 30 pF
NOTES: CL includes probe and jig capacitance All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 1.25 ns/V, tf 1.25 ns/V. The outputs are measured one at a time with one transition per measurement. VTT = VREF = VDDQ x 0.5
SW00838
Figure 1. Load circuitry
2002 Sep 27
7
Philips Semiconductors
Product data
14-bit SSTL_2 registered driver with differential clock inputs
SSTV16857
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
2002 Sep 27
8
Philips Semiconductors
Product data
14-bit SSTL_2 registered driver with differential clock inputs
SSTV16857
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 4.4 mm; lead pitch 0.4 mm
SOT480-1
D
E
A X
c y H
E
v
M
A
Z
48
25
Q A
2
(A 3)
A
1
A
pin 1 index L L
p
detail X
1
24
w e b
p M
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT A max. 1.10 A1 0.15 0.05 A2 0.95 0.85 A3 bp 0.23 0.13 c 0.20 0.09
D
(1)
E
(2)
e
HE 6.60 6.20
L
Lp 0.70 0.50
Q 0.40 0.30
v
w
y
Z
(1)
8 0
o o
mm
0.25
9.80 9.60
4.50 4.30
0.40
1.00
0.20
0.07
0.08
0.40 0.10
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC JEDEC MO-153 REFERENCES EIAJ EUROPEAN PROJECTION
ISSUE DATE
97-03-20 SOT480-1 99-12-27
2002 Sep 27
9
Philips Semiconductors
Product data
14-bit SSTL_2 registered driver with differential clock inputs
SSTV16857
VFBGA56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4.5 x 7 x 0.65 mm
SOT702-1
2002 Sep 27
10
Philips Semiconductors
Product data
14-bit SSTL_2 registered driver with differential clock inputs
SSTV16857
REVISION HISTORY Rev Date _6 2002 Sep 27
Description Product data (9397 750 10412); sixth version supersedes Product data fifth version, 2002 Jun 05. Engineering Change Notice: 853 2224 28989 (2002 Sep 26). Modifications: Package type changed from SSTV16857EC to SSTV16857EV. Product data (9397 750 09942); fifth version.
_5
2002 Jun 05
2002 Sep 27
11
Philips Semiconductors
Product data
14-bit SSTL_2 registered driver with differential clock inputs
SSTV16857
Data sheet status
Data sheet status [1] Objective data Preliminary data Product status [2] Development Qualification Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Product data
Production
[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2002 All rights reserved. Printed in U.S.A. Date of release: 09-02
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Document order number:
9397 750 10412
Philips Semiconductors
2002 Sep 27 12

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